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Until now the I2C PD was basically ignoring the very first sample, and
using that as the initial 'oldscl'/'oldsda' value.
However, if your logic analyzers trigger on, say, SDA=low that will
result in a file where the first sample is really important since it
is the one which the PD will need to know that there's a falling edge
on SDA.
Thus, assume both SCL and SDA are high/1 when the PD starts. This is
a good assumption since both pins have pullups on them in practice
and are thus high/1 when the bus is idle.
Later on we might want to have config options to let the PD assume
other states of SDA/SCL initially.
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