diff options
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/pca9571/pd.py | 23 | ||||
| -rw-r--r-- | decoders/tca6408a/pd.py | 18 |
2 files changed, 17 insertions, 24 deletions
diff --git a/decoders/pca9571/pd.py b/decoders/pca9571/pd.py index af0ad2d..a878142 100644 --- a/decoders/pca9571/pd.py +++ b/decoders/pca9571/pd.py @@ -56,24 +56,23 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' self.last_write = 0xFF # Chip port default state is high. - - self.logic_es = 1 - self.logic_data = [] - for i in range(NUM_OUTPUT_CHANNELS): - self.logic_data.append(bytes([1])) + self.last_write_es = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) +# def flush(self): +# self.put_logic_states() + def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) def put_logic_states(self): - if (self.es > self.logic_es): - for i in range(NUM_OUTPUT_CHANNELS): - self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) - self.logic_es = self.es + if (self.es > self.last_write_es): + data = bytes([self.last_write]) + self.put(self.last_write_es, self.es, self.out_logic, [0, data]) + self.last_write_es = self.es def handle_io(self, b): if self.state == 'READ DATA': @@ -83,14 +82,12 @@ class Decoder(srd.Decoder): '(%02X) are different' % self.last_write]]) else: operation = ['Outputs set', 'W'] +# self.put_logic_states() self.last_write = b + self.putx([1, [operation[0] + ': %02X' % b, operation[1] + ': %02X' % b]]) - for i in range(NUM_OUTPUT_CHANNELS): - bit = (b & (1 << i)) != 0 - self.logic_data[i] = bytes([bit]) - def check_correct_chip(self, addr): if addr != 0x25: self.putx([2, ['Warning: I²C slave 0x%02X not a PCA9571 ' diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 01c4e6d..0d63cc3 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -57,10 +57,8 @@ class Decoder(srd.Decoder): self.state = 'IDLE' self.chip = -1 - self.logic_es = 1 - self.logic_data = [] - for i in range(NUM_OUTPUT_CHANNELS): - self.logic_data.append(bytes([1])) + self.logic_output_es = 0 + self.logic_value = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -70,10 +68,10 @@ class Decoder(srd.Decoder): self.put(self.ss, self.es, self.out_ann, data) def put_logic_states(self): - if (self.es > self.logic_es): - for i in range(NUM_OUTPUT_CHANNELS): - self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) - self.logic_es = self.es + if (self.es > self.logic_output_es): + data = bytes([self.logic_value]) + self.put(self.logic_output_es, self.es, self.out_logic, [0, data]) + self.logic_output_es = self.es def handle_reg_0x00(self, b): self.putx([1, ['State of inputs: %02X' % b]]) @@ -81,9 +79,7 @@ class Decoder(srd.Decoder): def handle_reg_0x01(self, b): self.putx([1, ['Outputs set: %02X' % b]]) - for i in range(NUM_OUTPUT_CHANNELS): - bit = (b & (1 << i)) != 0 - self.logic_data[i] = bytes([bit]) + self.logic_value = b def handle_reg_0x02(self, b): self.putx([1, ['Polarity inverted: %02X' % b]]) |