diff options
Diffstat (limited to 'decoders/can')
| -rw-r--r-- | decoders/can/pd.py | 62 |
1 files changed, 41 insertions, 21 deletions
diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 54a9da6..ef1710b 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -101,7 +101,8 @@ class Decoder(srd.Decoder): return False # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. - self.putx([0, ['Stuff bit: %d' % self.rawbits[-1]]]) + self.putx([0, ['Stuff bit: %d' % self.rawbits[-1], + 'SB: %d' % self.rawbits[-1], 'SB']]) self.bits.pop() # Drop last bit. return True @@ -128,22 +129,25 @@ class Decoder(srd.Decoder): x = self.last_databit + 1 crc_bits = self.bits[x:x + 15 + 1] self.crc = int(''.join(str(d) for d in crc_bits), 2) - self.putb([0, ['CRC: 0x%04x' % self.crc]]) + self.putb([0, ['CRC sequence: 0x%04x' % self.crc, + 'CRC: 0x%04x' % self.crc, 'CRC']]) if not self.is_valid_crc(crc_bits): self.putb([0, ['CRC is invalid']]) # CRC delimiter bit (recessive) elif bitnum == (self.last_databit + 16): - self.putx([0, ['CRC delimiter: %d' % can_rx]]) + self.putx([0, ['CRC delimiter: %d' % can_rx, + 'CRC d: %d' % can_rx, 'CRC d']]) # ACK slot bit (dominant: ACK, recessive: NACK) elif bitnum == (self.last_databit + 17): ack = 'ACK' if can_rx == 0 else 'NACK' - self.putx([0, ['ACK slot: %s' % ack]]) + self.putx([0, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) # ACK delimiter bit (recessive) elif bitnum == (self.last_databit + 18): - self.putx([0, ['ACK delimiter: %d' % can_rx]]) + self.putx([0, ['ACK delimiter: %d' % can_rx, + 'ACK d: %d' % can_rx, 'ACK d']]) # Remember start of EOF (see below). elif bitnum == (self.last_databit + 19): @@ -151,7 +155,7 @@ class Decoder(srd.Decoder): # End of frame (EOF), 7 recessive bits elif bitnum == (self.last_databit + 25): - self.putb([0, ['End of frame', 'EOF']]) + self.putb([0, ['End of frame', 'EOF', 'E']]) self.reset_variables() return True @@ -163,13 +167,15 @@ class Decoder(srd.Decoder): # Bit 14: RB0 (reserved bit) # Has to be sent dominant, but receivers should accept recessive too. if bitnum == 14: - self.putx([0, ['RB0: %d' % can_rx]]) + self.putx([0, ['Reserved bit 0: %d' % can_rx, + 'RB0: %d' % can_rx, 'RB0']]) # Bit 12: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. rtr = 'remote' if self.bits[12] == 1 else 'data' - self.put12([0, ['RTR: %s frame' % rtr]]) + self.put12([0, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) # Remember start of DLC (see below). elif bitnum == 15: @@ -178,7 +184,8 @@ class Decoder(srd.Decoder): # Bits 15-18: Data length code (DLC), in number of bytes (0-8). elif bitnum == 18: self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) - self.putb([0, ['DLC: %d' % self.dlc]]) + self.putb([0, ['Data length code: %d' % self.dlc, + 'DLC: %d' % self.dlc, 'DLC']]) self.last_databit = 18 + (self.dlc * 8) # Remember all databyte bits, except the very last one. @@ -194,7 +201,8 @@ class Decoder(srd.Decoder): b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) ss = self.ss_databytebits[i * 8] es = self.ss_databytebits[((i + 1) * 8) - 1] - self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b)]]) + self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), + 'DB %d: 0x%02x' % (i, b), 'DB']]) self.ss_databytebits = [] elif bitnum > self.last_databit: @@ -212,28 +220,36 @@ class Decoder(srd.Decoder): # Bits 14-31: Extended identifier (EID[17..0]) elif bitnum == 31: self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) - self.putb([0, ['Extended ID: %d (0x%x)' % (self.eid, self.eid)]]) + s = '%d (0x%x)' % (self.eid, self.eid) + self.putb([0, ['Extended Identifier: %s' % s, + 'Extended ID: %s' % s, 'Extended ID', 'EID']]) self.fullid = self.id << 18 | self.eid - self.putb([0, ['Full ID: %d (0x%x)' % (self.fullid, self.fullid)]]) + s = '%d (0x%x)' % (self.fullid, self.fullid) + self.putb([0, ['Full Identifier: %s' % s, 'Full ID: %s' % s, + 'Full ID', 'FID']]) # Bit 12: Substitute remote request (SRR) bit - self.put12([0, ['SRR: %d' % self.bits[12]]]) + self.put12([0, ['Substitute remote request: %d' % self.bits[12], + 'SRR: %d' % self.bits[12], 'SRR']]) # Bit 32: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. if bitnum == 32: rtr = 'remote' if can_rx == 1 else 'data' - self.putx([0, ['RTR: %s frame' % rtr]]) + self.putx([0, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) # Bit 33: RB1 (reserved bit) elif bitnum == 33: - self.putx([0, ['RB1: %d' % can_rx]]) + self.putx([0, ['Reserved bit 1: %d' % can_rx, + 'RB1: %d' % can_rx, 'RB1']]) # Bit 34: RB0 (reserved bit) elif bitnum == 34: - self.putx([0, ['RB0: %d' % can_rx]]) + self.putx([0, ['Reserved bit 0: %d' % can_rx, + 'RB0: %d' % can_rx, 'RB0']]) # Remember start of DLC (see below). elif bitnum == 35: @@ -242,7 +258,8 @@ class Decoder(srd.Decoder): # Bits 35-38: Data length code (DLC), in number of bytes (0-8). elif bitnum == 38: self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) - self.putb([0, ['DLC: %d' % self.dlc]]) + self.putb([0, ['Data length code: %d' % self.dlc, + 'DLC: %d' % self.dlc, 'DLC']]) self.last_databit = 38 + (self.dlc * 8) # Remember all databyte bits, except the very last one. @@ -258,7 +275,8 @@ class Decoder(srd.Decoder): b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) ss = self.ss_databytebits[i * 8] es = self.ss_databytebits[((i + 1) * 8) - 1] - self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b)]]) + self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), + 'DB %d: 0x%02x' % (i, b), 'DB']]) self.ss_databytebits = [] elif bitnum > self.last_databit: @@ -285,7 +303,7 @@ class Decoder(srd.Decoder): # Bit 0: Start of frame (SOF) bit if bitnum == 0: if can_rx == 0: - self.putx([0, ['Start of frame', 'SOF']]) + self.putx([0, ['Start of frame', 'SOF', 'S']]) else: self.putx([1, ['Start of frame (SOF) must be a dominant bit']]) @@ -297,7 +315,8 @@ class Decoder(srd.Decoder): # The bits ID[10..4] must NOT be all recessive. elif bitnum == 11: self.id = int(''.join(str(d) for d in self.bits[1:]), 2) - self.putb([0, ['ID: %d (0x%x)' % (self.id, self.id)]]) + s = '%d (0x%x)' % (self.id, self.id), + self.putb([0, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) # RTR or SRR bit, depending on frame type (gets handled later). elif bitnum == 12: @@ -308,7 +327,8 @@ class Decoder(srd.Decoder): # Standard frame: dominant, extended frame: recessive elif bitnum == 13: ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' - self.putx([0, ['IDE: %s frame' % ide]]) + self.putx([0, ['Identifier extension bit: %s frame' % ide, + 'IDE: %s frame' % ide, 'IDE']]) # Bits 14-X: Frame-type dependent, passed to the resp. handlers. elif bitnum >= 14: |