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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2017-06-06 11:51:04 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2017-06-06 11:51:04 +0200 |
| commit | 18101a318c4ed6ed3f6a32ef7e4867ed7be1ff2a (patch) | |
| tree | eb3d82cf49a9ecc2f72577e8c93329e40d89f38c /decoders/tca6408a | |
| parent | 97b874bd0b6913ed52df1b8aac5e7491479fac9a (diff) | |
| download | libsigrokdecode-18101a318c4ed6ed3f6a32ef7e4867ed7be1ff2a.tar.gz libsigrokdecode-18101a318c4ed6ed3f6a32ef7e4867ed7be1ff2a.zip | |
Drop trailing whitespace in various PDs.
Diffstat (limited to 'decoders/tca6408a')
| -rw-r--r-- | decoders/tca6408a/pd.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 6d4be72..9fa9d23 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -91,7 +91,7 @@ class Decoder(srd.Decoder): return self.state = 'GET SLAVE ADDR' elif self.state == 'GET SLAVE ADDR': - self.chip = databyte + self.chip = databyte self.state = 'GET REG ADDR' elif self.state == 'GET REG ADDR': # Wait for a data write (master selects the slave register). |