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authorSoeren Apel <soeren@apelpie.net>2020-07-19 22:57:49 +0200
committerSoeren Apel <soeren@apelpie.net>2020-07-30 22:03:48 +0200
commit575124cd9e4e059cfe5f12fd047d6e8fa922cfbb (patch)
treefdd43709095e8bb1db23808f833eae3511fa812c /decoders/st25r39xx_spi/__init__.py
parenta43eba6af2ad18c7dc535f1c2b8764d13b5cd21a (diff)
downloadlibsigrokdecode-575124cd9e4e059cfe5f12fd047d6e8fa922cfbb.tar.gz
libsigrokdecode-575124cd9e4e059cfe5f12fd047d6e8fa922cfbb.zip
st25r39xx_spi: Minor style and description changes
Diffstat (limited to 'decoders/st25r39xx_spi/__init__.py')
-rw-r--r--decoders/st25r39xx_spi/__init__.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/decoders/st25r39xx_spi/__init__.py b/decoders/st25r39xx_spi/__init__.py
index d02dd7d..3803789 100644
--- a/decoders/st25r39xx_spi/__init__.py
+++ b/decoders/st25r39xx_spi/__init__.py
@@ -18,8 +18,11 @@
##
'''
-This decoder stacks on top of the 'spi' PD and decodes st25r3916 High performance NFC universal device and EMVCo reader
-(SPI mode) protocol.
+This decoder stacks on top of the SPI PD and decodes the st25r39xx High performance NFC universal device and EMVCo reader protocol (SPI mode).
+
+It has been successfully tested with the st25r3916, other chips of this family may or may not be fully supported but not been verified.
+
+Please note that the SPI interface uses clock polarity 0 and clock phase 1, which is not the default setting.
Details:
https://www.st.com/resource/en/datasheet/st25r3916.pdf